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19-3509; Rev 1; 11/05
Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C
General Description
The MAX9723 stereo DirectDriveTM headphone amplifier with BassMax and volume control is ideal for portable audio applications where space is at a premium and performance is essential. The MAX9723 operates from a single 1.8V to 3.6V power supply and includes features that reduce external component count, system cost, board space, and improves audio reproduction. The headphone amplifier uses Maxim's patented DirectDrive architecture that produces a ground-referenced output from a single supply, eliminating the need for large DC-blocking capacitors. The headphone amplifiers deliver 62mW into a 16 load, feature low 0.006% THD+N, and high 90dB PSRR. The MAX9723 features Maxim's industry-leading click-and-pop suppression. The BassMax feature boosts the bass response of the amplifier, improving audio reproduction when using inexpensive headphones. The integrated volume control features 32 discrete volume levels, eliminating the need for an external potentiometer. BassMax and the volume control are enabled through the I2C*/SMBusTMcompatible interface. Shutdown is controlled through either the hardware or software interfaces. The MAX9723 consumes only 3.7mA of supply current at 1.8V, provides short-circuit and thermal-overload protection, and is fully specified over the extended -40C to +85C temperature range. The MAX9723 is available in a tiny (2mm x 2mm x 0.62mm) 16-bump chip-scale package (UCSPTM) or 16-pin thin QFN (4mm x 4mm x 0.8mm) package.
Features
62mW, DirectDrive Headphone Amplifier Eliminates Bulky DC-Blocking Capacitors 1.8V to 3.6V Single-Supply Operation Integrated 32-Level Volume Control High 90dB PSRR at 1kHz Low 0.006% THD+N Industry-Leading Click-and-Pop Suppression 8kV HBM ESD-Protected Headphone Outputs Short-Circuit and Thermal-Overload Protection Low-Power Shutdown Mode (5A) Software-Enabled Bass Boost (BassMax) I2C/SMBus-Compatible Interface Available in Space-Saving, Thermally Efficient Packages: 16-Bump UCSP (2mm x 2mm x 0.62mm) 16-Pin Thin QFN (4mm x 4mm x 0.8mm)
MAX9723
Ordering Information
PART** MAX9723_EBE-T* MAX9723_ETE+ TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 16 UCSP-16 16 TQFN PKG CODE B16-1 T1644-4
Applications
PDA Audio Portable CD Players Mini Disc Players Automotive Multimedia MP3-Enabled Cellular Phones MP3 Players
**Replace the `_' with the one-letter code that denotes the slave address and maximum programmable gain. See the Selector Guide. +Denotes lead-free package. *Future product--contact factory for availability. Pin Configurations appear at end of data sheet.
Block Diagram
1.8V TO 3.6V SUPPLY
Selector Guide
PART MAX9723A MAX9723B MAX9723C MAX9723D SLAVE ADDRESS 1001100 1001101 1001100 1001101 MAXIMUM GAIN (dB) 0 0 +6 +6
SCL SDA
I2C INTERFACE
BBL
OUTL BassMax
*Purchase of I2C components from Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SMBus is a trademark of Intel Corp. UCSP is a trademark of Maxim Integrated Products, Inc.
INL INR VOLUME CONTROL
OUTR
BBR BassMax
MAX9723
________________________________________________________________ Maxim Integrated Products
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
ABSOLUTE MAXIMUM RATINGS
SGND to PGND .....................................................-0.3V to +0.3V VDD to PGND............................................................-0.3V to +4V PVSS to SVSS .........................................................-0.3V to +0.3V C1P to PGND..............................................-0.3V to (VDD + 0.3V) C1N to PGND............................................(PVSS - 0.3V) to +0.3V PVSS, SVSS to PGND ................................................+0.3V to -4V IN_ to SGND ..................................(SVSS - 0.3V) to (VDD + 0.3V) SDA, SCL to PGND ..................................................-0.3V to +4V SHDN to PGND ..........................................-0.3V to (VDD + 0.3V) OUT_ to SGND ............................................................-3V to +3V BB_ to SGND...............................................................-2V to +2V Duration of OUT_ Short Circuit to _GND ....................Continuous Continuous Current Into/Out of: VDD, C1P, PGND, C1N, PVSS, SVSS, or OUT_ ..............0.85A Any Other Pin.................................................................20mA Continuous Power Dissipation (TA = +70C) 4 x 4 UCSP (derate 8.2mW/C above +70C) ...........659.2mW 16-Pin Thin QFN (derate 16.9mW/C above +70C) ....1349mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Bump Temperature (soldering) Reflow ...........................................................................+230C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1F, BB_ = 0V. gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER GENERAL Supply Voltage Range Quiescent Supply Current Shutdown Supply Current Turn-On Time Turn-Off Time Thermal Shutdown Threshold Thermal Shutdown Hysteresis HEADPHONE AMPLIFIER Gain = 0dB, MAX9723A/ MAX9723B Gain = +6dB, MAX9723C/ MAX9723D 10 0.7 4.5 mV 0.8 17 10 DC, VDD = 1.8V to 3.6V f = 217Hz, 100mVP-P ripple, VDD = 3.0V f = 1kHz, 100mVP-P ripple, VDD = 3.0V f = 20kHz, 100mVP-P ripple, VDD = 3.0V 73 90 87 dB 86 61 5 27 100 k nA VDD IDD IDD_SHDN tON tOFF TTHRES THYST No load V SHDN = 0V 1.8 4 5 200 35 +143 12 3.6 6.5 8.5 V mA A s s C C SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Offset Voltage
VOS
Measured between OUT_ and SGND (Note 2)
Input Resistance BBR, BBL Input Bias Current
RIN IBIAS_BB
All volume levels
Power-Supply Rejection Ratio
PSRR
(Note 2)
2
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C
ELECTRICAL CHARACTERISTICS (continued)
(VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1F, BB_ = 0V. gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Output Power Total Harmonic Distortion Plus Noise SYMBOL POUT THD+N THD+N = 1%, fIN = 1kHz CONDITIONS RL = 32 RL = 16 (Note 5) 38 MIN TYP 59 60 0.006 0.004 0 -5 +6 +1 99 100 0.35 No sustained oscillations V = 0V, measured from OUT_ to ROUT_SHDN SHDN SGND COUT_SHDN VSHDN = 0V, measured from OUT_ to SGND Into shutdown Out of shutdown Into shutdown Out of shutdown 505 L to R or R to L, f = 10kHz, VOUT = 1VP-P, RL = 32, both channels loaded 300 20 60 -69 -71 dB -70 -69 600 700 kHz MAX9723C/ MAX9723D MAX UNITS mW % dB dB dB V/s pF k pF
MAX9723
RL = 16, POUT = 35mW, fIN = 1kHz RL = 32, POUT = 45mW, fIN = 1kHz MAX9723A/ MAX9723B Gain range bit 5 = 1 Gain range bit 5 = 0 Gain range bit 5 = 1 Gain range bit 5 = 0 BW = 22Hz to 22kHz A-weighted
Maximum Gain
AMAX
MAX9723C/ MAX9723D RL = 32, VOUT = 1VRMS
Signal-to-Noise Ratio Slew Rate Capacitive Drive Output Resistance in Shutdown Output Capacitance in Shutdown
SNR SR
Click/Pop Level
KCP
RL = 32, peak voltage, A-weighted, 32 samples per second (Notes 2, 4)
MAX9723A/ MAX9723B
Charge-Pump Switching Frequency Crosstalk DIGITAL INPUTS (SHDN, SDA, SCL) Input High Voltage Input Low Voltage Input Leakage Current DIGITAL OUTPUTS (SDA) Output Low Voltage Output High Current
fCP
XTALK
80
dB
VIH VIL
0.7 x VDD 0.3 x VDD 1
V V A V A
VOL IOH
IOL = 3mA VSDA = VDD
0.4 1
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
TIMING CHARACTERISTICS
(VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1F, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, see Timing Diagram.) (Notes 1, 3)
PARAMETER Serial Clock Frequency Bus Free Time Between a STOP and a START Condition START Condition Hold Time Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Maximum Rise Time of SDA and SCL Signals Maximum Fall Time of SDA and SCL Signals Setup Time for STOP Condition Pulse Width of Suppressed Spike Maximum Capacitive Load for Each Bus Line SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tSP CL_BUS 0.6 100 400 CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s s ns ns ns s ns pF
Note 1: Note 2: Note 3: Note 4:
All specifications are 100% tested at TA = +25C. Temperature limits are guaranteed by design. Inputs AC-coupled to SGND. Guaranteed by design. Headphone mode testing performed with a 32 resistive load connected to GND. Mode transitions are controlled by SHDN. The KCP level is calculated as: 20 x log [(level peak voltage during mode transition, no input signal)/(peak voltage under normal operation at rated power)]. Units are expressed in dB. Note 5: Output power MIN is specified at TA = +25C.
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
Typical Operating Characteristics
(VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1F, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. Outputs in phase, both channels loaded. TA = +25C, unless otherwise noted.) (See Functional Diagram/Typical Operating Circuit)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX9723 toc01
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX9723 toc02
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
VDD = 3V RL = 16
MAX9723 toc03
1 VDD = 2.4V RL = 16
1
VDD = 2.4V RL = 32
1
0.1 THD+N (%) THD+N (%)
0.1 THD+N (%) POUT = 10mW 0.01 POUT = 25mW
0.1 POUT = 20mW 0.01 POUT = 37mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 10 100 1k FREQUENCY (Hz) 10k 100k
POUT = 10mW 0.01
POUT = 23mW 0.001 10k 100k
0.001 10 100 1k FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX9723 toc04
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER
MAX9723 toc05
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER
VDD = 2.4V RL = 32 10
MAX9723 toc06
1
VDD = 3V RL = 32
100 VDD = 2.4V RL = 16 10
100
0.1 THD+N (%) THD+N (%) 1 fIN = 20Hz fIN = 1kHz fIN = 10kHz THD+N (%) 1 fIN = 1kHz fIN = 20Hz POUT = 10mW 0.01 0.01 POUT = 30mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 0 20 40 60 OUTPUT POWER (mW) 0.001 0 20 40 60 OUTPUT POWER (mW)
0.1
0.1
fIN = 10kHz
0.01
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER
MAX9723 toc07
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER
MAX9723 toc08
POWER DISSIPATION vs. OUTPUT POWER
160 POWER DISSIPATION (mW) 140 120 100 80 60 40 20 RL = 32 VDD = 2.4V fIN = 1kHz POUT = POUTL + POUTR OUTPUTS IN PHASE
MAX9723 toc09
100 VDD = 3V RL = 16 10
100 VDD = 3V RL = 32 10
180
RL = 16
THD+N (%)
1 fIN = 1kHz 0.1 fIN = 20Hz 0.01 fIN = 10kHz
THD+N (%)
1 fIN = 1kHz fIN = 20Hz 0.01 fIN = 10kHz
0.1
0.001 0 20 40 60 80 100 OUTPUT POWER (mW)
0.001 0 20 40 60 80 100 OUTPUT POWER (mW)
0 0 20 40 60 80 OUTPUT POWER (mW)
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
Typical Operating Characteristics (continued)
(VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1F, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. Outputs in phase, both channels loaded. TA = +25C, unless otherwise noted.) (See Functional Diagram/Typical Operating Circuit)
POWER DISSIPATION vs. OUTPUT POWER
MAX9723 toc10
OUTPUT POWER vs. LOAD RESISTANCE
70 OUTPUT POWER (mW) 60 50 40 30 THD+N = 1% 20 10 0 THD+N = 10% VDD = 2.4V fIN = 1kHz
MAX9723 toc11
300 250 POWER DISSIPATION (mW) 200 150 100 50 0 0
VDD = 3V fIN = 1kHz POUT = POUTL + POUTR OUTPUTS IN PHASE
80
RL = 16
RL = 32
20
40
60
80
100
120
10
100 LOAD RESISTANCE ()
1k
OUTPUT POWER (mW)
OUTPUT POWER vs. LOAD RESISTANCE
MAX9723 toc12
OUTPUT POWER vs. SUPPLY VOLTAGE
90 80 OUTPUT POWER (mW) 70 60 50 40 30 20 10 0 fIN = 1kHz RL = 16 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) THD+N = 1% THD+N = 10%
MAX9723 toc13
100 90 80 OUTPUT POWER (mW) 70 60 50 40 30 20 10 0 10 100 LOAD RESISTANCE () THD+N = 1% THD+N = 10% VDD = 3V fIN = 1kHz
100
1k
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX9723 toc14
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
-10 -20 -30 PSRR (dB) RL = 32
MAX9723 toc15
140 120 OUTPUT POWER (mW) 100 80 60 40 20 0 THD+N = 1% fIN = 1kHz RL = 32 THD+N = 10%
0
-40 -50 -60 -70 -80 -90 -100 10 100 1k FREQUENCY (Hz) 10k 100k
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V)
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
Typical Operating Characteristics (continued)
(VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1F, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. Outputs in phase, both channels loaded. TA = +25C, unless otherwise noted.) (See Functional Diagram/Typical Operating Circuit)
CROSSTALK vs. FREQUENCY
MAX9723 toc16
CROSSTALK vs. FREQUENCY
VIN = 1VP-P RL = 32 A = -10dB
MAX9723 toc17
0 -20 CROSSTALK (dB) -40 -60 -80 -100 -120 10 100 1k FREQUENCY (Hz) 10k RIGHT TO LEFT A = 0dB VIN = 1VP-P RL = 32 A = 0dB
0 -20 CROSSTALK (dB) -40 -60 -80 -100 -120 LEFT TO RIGHT A = -10dB 10 100 1k FREQUENCY (Hz) 10k RIGHT TO LEFT A = -10dB
LEFT TO RIGHT A = 0dB 100k
100k
BASS BOOST FREQUENCY RESPONSE
MAX9723 toc18
GAIN FLATNESS vs. FREQUENCY
0 -1 AMPLITUDE (dB) -2 -3 -4 -5 -6 -7
MAX9723 toc19
20 15 AMPLITUDE (dB) 10 5 0 -5 -10 10 100 1k FREQUENCY (Hz) 10k BassMax DISABLED R2 = 36k C3 = 0.068F R2 = 22k C3 = 0.1F R2 = 10k C3 = 0.22F NO LOAD R1 = 47k
1
100k
10
100
1k FREQUENCY (Hz)
10k
100k
OUTPUT SPECTRUM vs. FREQUENCY
MAX9723 toc20
CHARGE-PUMP OUTPUT VOLTAGE vs. OUTPUT CURRENT
NO HEADPHONE LOAD CHARGE-PUMP LOAD CONNECTED BETWEEN PVSS AND PGND
MAX9723 toc21
-40 -50 -60 AMPLITUDE (dBV) -70 -80 -90 -100 -110 -120 -130 -140 0 5 10 FREQUENCY (kHz) 15 RL = 32 VDD = 3V fIN = 1kHz
0 -0.5 OUTPUT VOLTAGE (V) -1.0 -1.5 -2.0 -2.5 -3.0 -3.5
20
0
25
50
75
100 125 150 175 200
OUTPUT CURRENT (mA)
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
Typical Operating Characteristics (continued)
(VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1F, BB_ = 0V, gain = 0dB, maximum volume, BassMax disabled. Load connected between OUT_ and SGND where specified. Outputs in phase, both channels loaded. TA = +25C, unless otherwise noted.) (See Functional Diagram/Typical Operating Circuit)
OUTPUT POWER vs. CHARGE-PUMP CAPACITANCE AND LOAD RESISTANCE
70 OUTPUT POWER (mW) 65 60 55 50 45 40 35 10 20 30 40 50 20ms/div LOAD RESISTANCE () C1 = C2 = 0.68F VOUT 10mV/div C1 = C2 = 2.2F C1 = C2 = 1F
MAX9723 toc22
POWER-UP/POWER-DOWN WAVEFORM
75
MAX9723 toc23
VDD 2V/div
VDD = 3V fIN = 1kHz THD+N = 1%
EXITING SHUTDOWN
MAX9723 toc24
ENTERING SHUTDOWN
MAX9723 toc25
VSHDN 2V/div
VSHDN 2V/div
VOUT_ 200mV/div
VOUT_ 200mV/div
40s/div
20s/div
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9723 toc26
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
7 SHUTDOWN CURRENT (A) 6 5 4 3 2 1 0 NO LOAD INPUTS GROUNDED 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V)
MAX9723 toc27
4.5
8
4.0 SUPPLY CURRENT (mA)
3.5
3.0
2.5 NO LOAD INPUTS GROUNDED 2.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V)
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C
Pin Description
PIN THIN QFN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EP BUMP UCSP D1 C1 B1 A1 B2 A2 A3 B3 A4 B4 C4 D4 C3 D3 D2 C2 -- NAME VDD C1P PGND C1N SCL PVSS SDA SHDN SGND INL INR SVSS BBR OUTR OUTL BBL EP FUNCTION Power-Supply Input. Bypass VDD to PGND with a 1F capacitor. Charge-Pump Flying Capacitor Positive Terminal Power Ground. Connect to SGND. Charge-Pump Flying Capacitor Negative Terminal Serial Clock Input. Connect a 10k pullup resistor from SCL to VDD. Charge-Pump Output. Connect to SVSS. Bypass PVSS with a 1F capacitor to PGND. Serial-Data Input. Connect a 10k pullup resistor from SDA to VDD. Shutdown. Drive SHDN low to disable the MAX9723. Connect SHDN to VDD while bit 7 is high for normal operation (see the Command Register section). Signal Ground. Connect to PGND. Left-Channel Input Right-Channel Input Headphone Amplifier Negative Power-Supply Input. Connect to PVSS. Right BassMax Input. Connect an external lowpass filter between OUTR and BBR to apply bass boost to the right-channel output. Connect BBR to SGND if BassMax is not used (see the BassMax (Bass Boost) section). Right Headphone Output Left Headphone Output Left BassMax Input. Connect an external lowpass filter between OUTL and BBL to apply bass boost to the right-channel output. Connect BBL to SGND if BassMax is not used (see the BassMax (Bass Boost) section). Exposed Paddle. Connect EP to SVSS or leave unconnected.
MAX9723
Detailed Description
The MAX9723 stereo headphone amplifier features Maxim's patented DirectDrive architecture, eliminating the large output-coupling capacitors required by conventional single-supply headphone amplifiers. The MAX9723 consists of two 62mW Class AB headphone amplifiers, hardware/software shutdown control, inverting charge pump, integrated 32-level volume control, BassMax circuitry, comprehensive click-and-pop suppression circuitry, and an I2C-compatible interface (see the Functional Diagram/Typical Operating Circuit). A negative power supply (PVSS) is created internally by inverting the positive supply (VDD). Powering the amplifiers from VDD and PVSS increases the dynamic range of the amplifiers to almost twice that of other single-supply amplifiers, increasing the total available output power.
The MAX9723 DirectDrive outputs are biased at SGND (see Figure 1). The benefit of this 0V bias is that the amplifier outputs do not have a DC component, eliminating the need for large DC-blocking capacitors. Eliminating the DC-blocking capacitors on the output saves board space, system cost, and improves low-frequency response. An I2C-compatible interface allows serial communication between the MAX9723 and a microcontroller. The MAX9723 is available with two different I2C addresses allowing two MAX9723 ICs to share the same bus (see Table 1). The internal command register controls the shutdown status of the MAX9723, enables the BassMax circuitry, sets the maximum gain of the amplifier, and sets the volume level (see Table 2). The MAX9723's BassMax circuitry improves audio reproduction by boosting the bass response of the amplifier, compensating for any low-frequency attenuation introduced by
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
VDD VDD/2 GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD
In addition to the cost and size disadvantages, the DCblocking capacitors required by conventional headphone amplifiers limit low-frequency response and can distort the audio signal. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues: 1) The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. The DirectDrive output biasing scheme allows the sleeve to be grounded. 2) During an ESD strike, the amplifier's ESD structure is the only path to system ground. The amplifier must be able to withstand the full ESD strike. The MAX9723 headphone outputs can withstand an 8kV ESD strike (HBM). 3) When using the headphone jack as a line out to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. The DirectDrive outputs of the MAX9723 can be directly coupled to other ground-biased equipment.
SGND
-VDD DirectDrive BIASING SCHEME
Figure 1. Traditional Amplifier Output vs. MAX9723 DirectDrive Output
the headphone. The MAX9723A and MAX9723B have a maximum amplifier gain of 0dB while the MAX9723C and MAX9723D have a maximum gain of +6dB. Amplifier volume is digitally programmable to any one of 32 levels.
Charge Pump
The MAX9723 features a low-noise charge pump. The 600kHz switching frequency is well beyond the audio range, and does not interfere with the audio signals. This enables the MAX9723 to achieve a 99dB SNR. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. Limiting the switching speed of the charge pump minimizes di/dt noise caused by the parasitic bond wire and trace inductance. Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the size of C2 (see the Functional Diagram/Typical Operating Circuit).
DirectDrive
Traditional single-supply headphone amplifiers have their outputs biased at a nominal DC voltage, typically half the supply, for maximum dynamic range. Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. Maxim's patented DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the MAX9723 headphone amplifier outputs to be biased at 0V, almost doubling the dynamic range while operating from a single supply. With no DC component, there is no need for the large DC-blocking capacitors. Instead of two large (typically 220F) tantalum capacitors, the MAX9723 charge pump requires only two small 1F ceramic capacitors, thereby conserving board space, reducing cost, and improving the low-frequency response of the headphone amplifier. See the Output Power vs. Charge-Pump Capacitance and Load Resistance graph in the Typical Operating Characteristics for details of the possible capacitor sizes.
10
Shutdown
The MAX9723 features a 5A, low-power shutdown mode that reduces quiescent current consumption and extends battery life. Shutdown is controlled by a hardware or software interface. Driving SHDN low disables the drive amplifiers, bias circuitry, charge pump, and sets the headphone amplifier output impedance to 20k. Similarly, the MAX9723 enters shutdown when bit seven (B7) in the control register is reset. SHDN and B7 must be high to enable the MAX9723. The I2C interface is active and the contents of the command register are not affected when in shutdown. This allows the master to write to the MAX9723 while in shutdown.
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C
Click-and-Pop Suppression
The output-coupling capacitor is a major contributor of audible clicks and pops in conventional single-supply headphone amplifiers. The amplifier charges the coupling capacitor to its output bias voltage at startup. During shutdown the capacitor is discharged. This charging and discharging results in a DC shift across the capacitor, which appears as an audible transient at the speaker. Since the MAX9723 headphone amplifier does not require output-coupling capacitors, no audible transients occur. Additionally, the MAX9723 features extensive click-andpop suppression that eliminates any audible transient sources internal to the device. The Power-Up/PowerDown Waveform in the Typical Operating Characteristics shows that there are minimal transients at the output upon startup or shutdown. In most applications, the preamplifier driving the MAX9723 has a DC bias of typically half the supply. The input-coupling capacitor is charged to the preamplifier's bias voltage through the MAX9723's input impedance (RIN) during startup. The resulting voltage shift across the capacitor creates an audible click/pop. To avoid clicks/pops caused by the input filter, delay the rise of SHDN by at least 4 time constants, 4 x RIN x CIN, relative to the start of the preamplifier.
MAX9723
MAX9723
R AUDIO INPUT
R
OUT_
R1 BB_ BassMax ENABLE
R2
C3
Figure 2. BassMax External Connections
using positive feedback from OUT_ to BB_. Figure 2 shows the connections needed to implement BassMax.
Maximum Gain Control
The MAX9723A and MAX9723B have selectable maximum gains of -5dB or 0dB (see Table 5) while the MAX9723C and MAX9723D have selectable maximum gains of +1dB or +6dB (see Table 6). Bit 5 in the command register selects between the two maximum gain settings.
BassMax (Bass Boost)
Typical headphones do not have a flat-frequency response. The small physical size of the diaphragm does not allow the headphone speaker to efficiently reproduce low frequencies. This physical limitation results in attenuated bass response. The MAX9723 includes a bass boost feature that compensates for the headphone's poor bass response by increasing the amplifier gain at low frequencies. The DirectDrive output of the MAX9723 has more headroom than typical single-supply headphone amplifiers. This additional headroom allows boosting the bass frequencies without the output-signal clipping. Program the BassMax gain and cutoff frequency with external components connected between OUT_ and BB_ (see the Functional Diagram/Typical Operating Circuit). Use the I2C-compatible interface to program the command register to enable/disable the BassMax circuit. BB_ is connected to the noninverting input of the output amplifier when BassMax is enabled. BB_ is pulled to SGND when BassMax is disabled. The typical application of the BassMax circuit involves feeding a lowpass version of the output signal back to the amplifier. This is realized
Volume Control
The MAX9723 includes a 32-level volume control that adjusts the gain of the output amplifiers according to the code contained in the command register. Volume is programmed through the command register bits [4:0]. Tables 7-10 show all of the available gain settings for the MAX9723A-MAX9723D. The mute attenuation is typically better than 100dB when driving a 32 load.
Serial Interface
The MAX9723 features an I 2 C/SMBus-compatible, 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the MAX9723 and the master at clock rates up to 400kHz. Figure 3 shows the 2-wire interface timing diagram. The MAX9723 is a receive-only slave device relying on the master to generate the SCL signal. The MAX9723 cannot write to the SDA bus except to acknowledge the receipt of data
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11
Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tBUF tHD, STA tSP tSU, STO
Figure 3. 2-Wire Serial-Interface Timing Diagram
from the master. The master, typically a microcontroller, generates SCL and initiates data transfer on the bus. A master device communicates to the MAX9723 by transmitting the proper address followed by the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX9723 SDA line operates as both an input and an open-drain output. A pullup resistor, greater than 500, is required on the SDA bus. The MAX9723 SCL line operates as an input only. A pullup resistor, greater than 500, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9723 from highvoltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. Start and Stop Conditions SDA and SCL idle high when the bus is not in use. A master device initiates communication by issuing a
12
START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 4). A START condition from the master signals the beginning of transmission to the MAX9723. The master terminates transmission and frees the bus by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX9723 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. Slave Address The MAX9723 is available with one of two preset slave addresses (see Table 1). The address is defined as the seven most significant bits (MSBs) followed by the Read/Write (R/W) bit. The address is the first byte of information sent to the MAX9723 after the START condition. The MAX9723 is a slave device only capable of being written to. The sent R/W bit must always be a zero when configuring the MAX9723. The MAX9723 acknowledges the receipt of its address even if R/W is set to 1. However, the MAX9723 will not drive SDA. Addressing the MAX9723 with R/W set to 1 causes the master to receive all 1's regardless of the contents of the command register. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9723 uses to handshake receipt of each byte of
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
S Sr P
START CONDITION SCL 1 2 CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
8 NOT ACKNOWLEDGE
9
SDA
SDA ACKNOWLEDGE
Figure 4. START, STOP, and REPEATED START Conditions
Figure 5. Acknowledge
Table 1. MAX9723 Address Map
PART MAX9723A MAX9723B MAX9723C MAX9723D MAX9723 SLAVE ADDRESS A6 1 1 1 1 A5 0 0 0 0 A4 0 0 0 0 A3 1 1 1 1 A2 1 1 1 1 A1 0 0 0 0 A0 0 1 0 1 R/W 0 0 0 0
Table 3. Shutdown Control, SHDN = 1
MODE MAX9723 Disabled MAX9723 Enabled B7 0 1
Table 4. BassMax Control
MODE BassMax Disabled BassMax Enabled B6 0 1
Table 2. MAX9723 Command Register
B7 SHUTDOWN B6 BassMax ENABLE B5 MAXIMUM GAIN B4 B3 B2 B1 B0 VOLUME
data (see Figure 5). The MAX9723 pulls down SDA during the master-generated 9th clock pulse. The SDA line must remain stable and low during the high period of the acknowledge clock pulse. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may reattempt communication. Write Data Format A write to the MAX9723 includes transmission of a START condition, the slave address with the R/W bit reset to 0 (see Table 1), one byte of data to configure the command register, and a STOP condition. Figure 6 illustrates the proper format for one frame. The MAX9723 only accepts write data, but it acknowledges the receipt of its address byte with the R/W bit set high. The MAX9723 does not write to the SDA bus in the event that the R/W bit is set high. Subsequently,
the master reads all 1's from the MAX9723. Always reset the R/W bit to 0 to avoid this situation. Command Register The MAX9723 has one command register that is used to enable/disable shutdown, enable/disable BassMax, and set the maximum gain and volume. Table 2 describes the function of the bits contained in the command register. Reset B7 to 0 to shut down the MAX9723. The MAX9723 wakes up from shutdown when B7 is set to 1 provided SHDN is high. SHDN must be high and B7 must be set to 1 for the MAX9723 to operate normally (see Table 3). Set B6 to 1 to enable BassMax (see Table 4). The output signal's low-frequency response will be boosted according to the external components connected between OUT_ and BB_. See the BassMax Gain-Setting Components section in the Applications Information section for details on choosing the external components.
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
Table 5. MAX9723A and MAX9723B Maximum Gain Control
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION ACKNOWLEDGE FROM MAX9723 S SLAVE ADDRESS R/W 0 ACK COMMAND BYTE ACKNOWLEDGE FROM MAX9723 ACK P
MAXIMUM GAIN (dB)
B7 B6 B5 B4 B3 B2 B1 B0
B5 0 1
-5 0
Table 6. MAX9723C and MAX9723D Maximum Range Control
MAXIMUM GAIN (dB) +1 +6 B5 0 1
Figure 6. Write Data Format Example
The MAX9723A and MAX9723B have a maximum gain setting of -5dB or 0dB, while the MAX9723C and MAX9723D have a maximum gain setting of +1dB or +6dB. B5 in the command register programs the maximum gain (see Tables 5 and 6). Adjust the MAX9723's amplifier gain with the volume control bits [4:0]. The gain is adjustable to one of 32 steps ranging from full mute to the maximum gain programmed by B5. Tables 7-10 list all the possible gain settings for the MAX9723. Figures 7-10 show the volume control transfer functions for the MAX9723. Power-On Reset The contents of the MAX9723's command register at power-on are shown in Table 11.
tion, reduce VDD, increase load impedance, decrease the ambient temperature, or add heatsinking. Large output, supply, and ground traces decrease JA, allowing more heat to be transferred from the package to surrounding air.
Output Dynamic Range
Dynamic range is the difference between the noise floor of the system and the output level at 1% THD+N. It is essential that a system's dynamic range be known before setting the maximum output gain. Output clipping will occur if the output signal is greater than the dynamic range of the system. The DirectDrive architecture of the MAX9723 has increased dynamic range compared to other single-supply amplifiers. Use the THD+N vs. Output Power in the Typical Operating Characteristics to identify the system's dynamic range. Find the output power that causes 1% THD+N for a given load. This point will indicate what output power causes the output to begin to clip. Use the following equation to determine the peak output voltage that causes 1% THD+N for a given load. VOUT _(P-P) = 2 2(POUT _ 1% x RL ) where POUT_1% is the output power that causes 1% THD+N, RL is the load resistance, and VOUT_(P-P) is the peak output voltage. After V OUT_(P-P) is identified, determine the peak input voltage that can be amplified without clipping: VOUT _(P-P) VIN _(P-P) = 10 20 where VIN_(P-P) is the largest peak voltage that can be amplified without clipping, and AV is the voltage gain of
AV
Applications Information
Power Dissipation and Heat Sinking
Linear power amplifiers can dissipate a significant amount of power under normal operating conditions. The maximum power dissipation for each package is given in the Absolute Maximum Ratings section under Continuous Power Dissipation or can be calculated by the following equation: PD(MAX) = TJ(MAX) - TA JA
where TJ(MAX) is +150C, TA is the ambient temperature, and JA is the reciprocal of the derating factor in C/W as specified in the Absolute Maximum Ratings section. For example, JA for the thin QFN package is +59C/W. The MAX9723 has two power dissipation sources, the charge pump and the two output amplifiers. If the power dissipation exceeds the rated package dissipa14
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
Table 7. MAX9723A and MAX9723B Gain Settings (Bit 5 = 1, Max Gain = 0dB)
B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 (LSB) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN (dB) 0 -0.5 -1 -1.5 -2 -2.5 -3 -4 -5 -6 -7 -9 -11 -13 -15 -17 -19 -21 -23 -25 -27 -29 -31 -33 -35 -37 -39 -41 -43 -45 -47 MUTE
Table 8. MAX9723A and MAX9723B Gain Settings (B5 = 0, Max Gain = -5dB)
B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 (LSB) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN (dB) -5 -6 -7 -9 -11 -13 -15 -17 -19 -21 -23 -25 -27 -29 -31 -33 -35 -37 -39 -41 -43 -45 -47 -51 -55 -59 -63 -67 -71 -75 -79 MUTE
the amplifier in dB determined by the maximum gain setting (Bit 5) or the combination of the maximum gain setting plus bass boost (see the BassMax Gain-Setting Components section).
Component Selection
Input-Coupling Capacitor The AC-coupling capacitor (CIN) and internal gain-setting resistor form a highpass filter that removes any DC bias from an input signal (see the Functional Diagram/ Typical Operating Circuit). CIN allows the MAX9723 to bias the signal to an optimum DC level. The -3dB point
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
Table 9. MAX9723C and MAX9723D Gain Settings (B5 = 1, Max Gain = +6dB)
B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 (LSB) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN (dB) 6 5.5 5 4.5 4 3.5 3 2 1 0 -1 -3 -5 -7 -9 -11 -13 -15 -17 -19 -21 -23 -25 -27 -29 -31 -33 -35 -37 -39 -41 MUTE
Table 10. MAX9723C and MAX9723D Gain Settings (B5 = 0, Max Gain = +1dB)
B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B0 (LSB) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN (dB) 1 0 -1 -3 -5 -7 -9 -11 -13 -15 -17 -19 -21 -23 -25 -27 -29 -31 -33 -35 -37 -39 -41 -45 -49 -53 -57 -61 -65 -69 -73 MUTE
of the highpass filter, assuming zero-source impedance, is given by: f-3dB = 1 2 x RIN x CIN
Table 11. Initial Power-Up Command Register Status
MODE Power-On Reset B7 1 B6 1 B5 1 B4 1 B3 1 B2 1 B1 1 B0 1
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
MAX9723A AND MAX9723B TRANSFER FUNCTION (BIT 5 = 1)
10 0 -20 -10 GAIN (dB) GAIN (dB) -20 -30 -40 -80 -50 0 6 12 18 CODE 24 30 -90 0 6 12 18 CODE 24 30 -30 -40 -50 -60 -70 0 -10
MAX9723A AND MAX9723B TRANSFER FUNCTION (BIT 5 = 0)
Figure 7. MAX9723A/MAX9723B Transfer Function with Bit 5 = 1
Figure 8. MAX9723A/MAX9723B Transfer Function with Bit 5 = 0
MAX9723C AND MAX9723D TRANSFER FUNCTION (BIT 5 = 1)
10 0 -10 -20 GAIN (dB) -30 -40 -50 -60 -40 -70 -80 0 6 12 18 CODE 24 30 -50 0 GAIN (dB) 0 -10 -20 -30 10
MAX9723C AND MAX9723D TRANSFER FUNCTION (BIT 5 = 0)
6
12
18 CODE
24
30
Figure 9. MAX9723C/MAX9723D Transfer Function with Bit 5 = 1
Figure 10. MAX9723C/MAX9723D Transfer Function with Bit 5 = 0
where RIN is a minimum of 10k. Choose CIN such that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high affects the amplifier's low-frequency response. Use capacitors with low-voltage coefficient dielectrics. Film or C0G dielectric capacitors are good choices for AC-coupling capacitors. Capacitors with high-voltage coefficients, such as ceramics, can result in increased distortion at low frequencies.
Charge-Pump Flying Capacitor The charge-pump flying capacitor connected between C1N and C1P affects the charge pump's load regulation and output impedance. Choosing a flying capacitor that is too small degrades the MAX9723's ability to provide sufficient current drive and leads to a loss of output voltage. Increasing the value of the flying capacitor improves load regulation and reduces the chargepump output impedance. See the Output Power vs.
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C
GAIN PROFILE WITH AND WITHOUT BassMax
10 8 6 4 AV (dB) 2 0 -2 -4 -6 -8 -10 1 10 100 FREQUENCY (Hz) 1k 10k WITHOUT BassMax MAX9723A CMD REGISTER CODE = 0xFF R1 = 47k R2 = 22k C3 = 0.1F WITH BassMax fPOLE fZERO
To maintain circuit stability, the ratio: R2/(R1 + R2) must not exceed 1/2. A ratio equaling 1/3 is recommended. The switch that shorts BB_ to SGND, when BassMax is disabled, can have an on-resistance as high as 300. Choose a value for R1 that is greater than 40k to ensure that positive feedback is negligible when BassMax is disabled. Table 12 contains a list of R2 values, with R1 = 47k, and the corresponding lowfrequency gain. The low-frequency boost attained by the BassMax circuit is added to the gain realized by the volume setting. Select the BassMax gain so that the output signal will remain within the dynamic range of the MAX9723. Output signal clipping will occur at low frequencies if the BassMax gain boost is excessively large (see the Output Dynamic Range section). Capacitor C3 forms a pole and a zero according to the following equations: R1- R2 2 x C3 x R1x R2 R1+ R2 fZERO = 2 x C3 x R1x R2 fPOLE = fPOLE is the frequency at which the gain boost begins to roll off. fZERO is the frequency at which the bassboost gain no longer affects the transfer function and the volume-control gain dominates. Table 13 contains a list of capacitor values and the corresponding poles and zeros for a given DC gain. See Figure 11 for an example of a gain profile using BassMax.
MAX9723
Figure 11. BassMax, Gain Profile Example
Charge-Pump Capacitance and Load Impedance graph in the Typical Operating Characteristics. Charge-Pump Hold Capacitor The hold capacitor's value and ESR directly affect the ripple at PVSS. Ripple is reduced by increasing the value of the hold capacitor. Choosing a capacitor with lower ESR reduces ripple and output impedance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Charge-Pump Capacitance and Load Impedance graph in the Typical Operating Characteristics. BassMax Gain-Setting Components The bass-boost low-frequency response, when BassMax is enabled, is set by the ratio of R1 to R2 by the following equation (see Figure 2): A V _ BOOST = 20 x log R1 + R2 R1 - R2
Custom Maximum Gain Setting Using BassMax
The circuit in Figure 12 uses the BassMax function to increase the maximum gain of the MAX9723. The gain boost created with the circuit in Figure 12 is added to the maximum gain selected by Bit 5 in the command register. Set the maximum gain with RA and RB using the following equation: RA + RB AV _ TOTAL = AV _ VOL + 20 x log RA - RB where AV_VOL is the gain due to the volume setting, and AV_TOTAL is the absolute passband gain in dB. Capacitor CA blocks any DC offset from being gained, but allows higher frequencies to pass. CA creates a pole that indicates the low-frequency point of the pass band. Choose CA so that the lowest frequencies of
where AV_BOOST is the voltage gain boost in dB at low frequencies. AV_BOOST is added to the gain realized by the volume setting. The absolute gain at low frequencies is equal to: A V _ TOTAL = A V _ VOL + A V _ BOOST where AV_VOL is the gain due to the volume setting, and AV_TOTAL is the absolute gain at low frequencies.
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
FREQUENCY RESPONSE OF FIGURE 12
10
MAX9723
R
R
9 8
AV (dB)
AUDIO INPUT OUT_ CA RA BassMax ENABLE
7 6 5 4 3 2 BB_ RB 1 0 0.1 1 10 100 1k 10k FREQUENCY (Hz) MAX9723A CMD REGISTER CODE = 0xFF RA = 47k RB = 22k CA = 0.33F
Figure 12. Using BassMax to Increase MAX9723's Maximum Gain
Figure 13. Increasing the Maximum Gain Using BassMax
Table 12. BassMax Gain Examples (R1 = 47k)
R2 (k) 39 33 27 22 15 10 AV GAIN (dB) 20.6 15.1 11.3 8.8 5.7 3.7
interest are not attenuated. For a typical application, set fPOLE equal to or below 20Hz. CA = 1 2 fPOLE x (RA - RB)
Figure 13 shows the frequency response of the circuit in Figure 12. With RA = 47k, RB = 22k, and CA = 0.33F, the passband gain is set to 8.8dB.
Layout and Grounding
Proper layout and grounding are essential for optimum performance. Connect PGND and SGND together at a single point on the PC board. Connect PVSS to SVSS and bypass with a 1F capacitor to PGND. Bypass VDD to PGND with a 1F capacitor. Place the power-supply bypass capacitor and the charge-pump capacitors as close to the MAX9723 as possible. Route PGND and all traces that carry switching transients away from SGND and the audio signal path. Route digital signal traces away from the audio signal path. Make traces perpendicular to each other when routing digital signals over or under audio signals. The thin QFN package features an exposed paddle that improves thermal efficiency. Ensure that the exposed paddle is electrically isolated from PGND, SGND, and V DD. Connect the exposed paddle to SV SS when the board layout dictates that the exposed paddle cannot be left floating.
Table 13. BassMax Pole and Zero Examples for a Gain Boost of 8.8dB (R1 = 47k, R2 = 22k)
C3 (nF) 100 82 68 56 47 22 10 fPOLE (Hz) 38 47 56 68 81 174 384 fZERO (Hz) 106 130 156 190 230 490 1060
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
Functional Diagram/Typical Operating Circuit
1.8V TO 3.6V ANALOG INPUT
C5 1F VDD SCL
R5 10k SDA
R6 10k INR
CIN 0.47F
R VDD VDD R OUTR SVSS SVSS RBB R4 22k VDD LBB R2 22k C3 0.1F C4 0.1F R3 47k
I2C INTERFACE SHDN
MAX9723
VDD C1P C1 1F C1N CHARGE PUMP
VDD
SVSS R SVSS SGND PGND PVSS SVSS C2 1F INL CIN 0.47F R BASS BOOST CIRCUIT TUNED FOR +8.8dB AT 106Hz. OUTL
R1 47k
ANALOG INPUT
UCSP Applications Information
For the latest application details on UCSP construction, dimensions, tape carrier information, PC board techniques, bump-pad layout , and recommended reflow temperature profile, as well as the latest information on reliability testing results, go to Maxim's website at www.maxim-ic.com/ucsp and look up the Application Note: UCSP-A Wafer-Level Chip-Scale Package.
Chip Information
TRANSISTOR COUNT: 7165 PROCESS: BiCMOS
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C
System Diagram
R5 10k R6 10k 1.8V TO 3.6V C5 1F VDD SDA I2C MASTER SCL CIN 0.47F INL CODEC CIN 0.47F INR LBB R4 22k C4 0.1F OUTL R3 47k
MAX9723
MAX9723
C1P C1 1F C1N
OUTR R1 47k RBB PVSS C2 1F SVSS PGND SGND R2 22k C3 0.1F
Pin Configurations
TOP VIEW (BUMP SIDE DOWN) 1 2 3 4
12 A C1N PVSS SDA SGND BBR OUTR B PGND SCL SHDN INL OUTL BBL 13 14 15 16 1
VDD
11
10
SGND
SVSS
TOP VIEW
INR
INL
9 8 7 SHDN SDA
PVSS
MAX9723_
6 5
SCL
MAX9723_
C C1P BBL BBR
INR
2
C1P
3
PGND
4
C1N
THIN QFN
D
VDD OUTL OUTR SVSS
UCSP
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C MAX9723
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
1
2
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2
2
22
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Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
16L,UCSP.EPS
MAX9723
PACKAGE OUTLINE, 4x4 UCSP 21-0101 H
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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